{"id":5461,"date":"2024-09-24T17:13:26","date_gmt":"2024-09-24T22:13:26","guid":{"rendered":"https:\/\/www.darkreading.com\/endpoint-security\/security-concerns-dog-emerging-chip-architecture"},"modified":"2024-09-24T17:13:26","modified_gmt":"2024-09-24T22:13:26","slug":"security-concerns-plague-emerging-chip-architecture","status":"publish","type":"post","link":"https:\/\/ddi.mohflo.net\/index.php\/2024\/09\/24\/security-concerns-plague-emerging-chip-architecture\/","title":{"rendered":"Security Concerns Plague Emerging Chip Architecture"},"content":{"rendered":"
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An emerging chip architecture gaining traction in smartphones, automotive technologies, and other electronics may find adoption stymied by security concerns.<\/span><\/p>\n

Using x86 and ARM processors for hardware development can get expensive because of royalties that have to be paid to the owners (Intel and Arm). RISC-V is an instruction set on which customers can personalize silicon chips to meet their needs, much like how Lego blocks are put together. RISC-V is open and free to license, so anyone can design, manufacture, and sell RISC-V chips and software.<\/span><\/p>\n

RISC-V is drawing interest among companies in the auto, critical infrastructure, and industrial sectors. For example, NASA is creating chips based on RISC-V that it intends to use in its space programs. <\/span>Omdia estimates<\/a><\/span> RISC-V shipments could tally 17 billion processors in 2030, improving 50% every year starting in 2024.<\/span><\/p>\n

“46% of those processors are expected to be found in industrial applications, although the biggest growth over the forecast period will come in the automotive segment,” Omdia said.<\/span><\/p>\n

Vulnerabilities in Designs<\/h2>\n

RISC-V’s open-source ethos is its biggest advantage, but also a liability: bad actors could introduce backdoors in the chip designs. Vulnerabilities in RISC-V chips used in automotive technology or critical infrastructure could be disastrous.<\/span><\/p>\n

At Black Hat USA in August, researchers disclosed <\/span>Ghostwrite<\/a><\/span>, which allows users to bypass memory protection and access privileged memory in a RISC-V chip design called Xuantie C910. The Xuantie C910, designed by T-Head, a subsidiary of China-based Alibaba Group, received a lot of publicity when it was launched three years ago. It was one of the earliest RISC-V processors with a vector extension, which helps CPUs run demanding applications that include AI.<\/span><\/p>\n

The vulnerability is particularly concerning because it affects the chip’s proprietary vector extension, which wasn’t properly implemented, says Fabian Thomas, a researcher in the group at <\/span>CISPA Helmholtz Center for Information Security<\/a><\/span> that discovered GhostWrite. Chip makers can patch the C910 by disabling the vector extension, but it will still be difficult to implement.<\/span><\/p>\n

“People bought it and built 64-core machines because of that, and now we have to tell them to disable it,” Thomas says.<\/span><\/p>\n

Shared Designs, Hard to Patch<\/h2>\n

The issue is not in the RISC-V architecture itself, but in a faulty silicon implementation. Chip designers are enthusiastic about sharing RISC-V designs, but this means that designs with vulnerabilities may potentially be replicated and used in various areas. Resulting devices could be vulnerable to attack, and may be difficult to patch with microcode updates.<\/span><\/p>\n

“The digital transformation happening in these sectors means they’re all connected now, creating potential to exploit across all these very safety-critical systems,” says Margaret Schmitt, a hardware security consultant.<\/span><\/p>\n

It’s already difficult to fix hardware vulnerabilities with firmware updates. The open nature of this chip architecture means it will be difficult to fix them in the field. “The silicon vulnerability is worse because you can’t really fix them in the field in many cases… if it connects to critical infrastructure, this could be seen forever,” says Alex Matrosov, CEO at Binarly.io.<\/span><\/p>\n

There are hundreds of RISC-V designs available on GitHub to pick up, but security teams need to consider the risks of winding up with malicious chip designs with backdoors. “This is similar to open-source software projects where people [make] changes, saying ‘I’m making it better,’ but it’s actually a backdoor or malware,” Schmitt says.<\/span><\/p>\n

The concern is especially heightened as the RISC-V architecture has become a priority for Russia and China, which are investing heavily in the technology to build homegrown chips. China and Russia ramped up RISC-V adoption after the U.S. banned the export of advanced chips to these countries amid trade and political hostilities.<\/span><\/p>\n

The U.S. government has already talked about limiting RISC-V access to China, though that may be hard to do as the architecture is open source.<\/span><\/p>\n

“You’re seeing a potential basis for China to use this, a potential for unintended or intentionally added weaknesses to be a serious concern,” says Schmitt.<\/span><\/p>\n

Working With Security Partners<\/h2>\n

Organizations working with RISC-V chips on a shoestring budget may make the decision to sacrifice security, says Mike Eftimakis, vice president of strategy and ecosystem at Codasip, a software company.<\/span><\/p>\n

“To be able to find a bug, you have to have the infrastructure behind you. It’s very expensive and requires specialized knowledge, so it naturally shrinks the base of people who could potentially help with the verification of these devices,” Eftimakis says.<\/span><\/p>\n

Hardware security experts recommended going to established RISC-V companies with solid security processes, a strong customer base, and a good track record of designing chips. One example is Santa Clara, Calif.-based SiFive, which handles security analysis and rigorous compliance testing in its cores. The company has a large customer base that includes Google and NASA, a spokesman said in an email.<\/span><\/p>\n

Another RISC-V company, Cupertino, Calif-based Ventana Micro Systems, uses the <\/span>Caliptra specification<\/a><\/span> to put security features directly in computing chips. Caliptra was developed by the Open Compute Project, a coalition which includes Google, Microsoft, AMD, and Nvidia.<\/span><\/p>\n

Ventana Micro leaders have extensive experience working with x86 and ARM architectures, and are using that experience to secure RISC-V chips. “We applied these learnings during our ground-up development and have many patented features targeted at making our microarchitecture resilient to attacks,” a company spokesperson said in an email.<\/span><\/p>\n

Source<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

An emerging chip architecture gaining traction in smartphones, automotive technologies,<\/p>\n","protected":false},"author":12,"featured_media":5462,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[1],"tags":[809],"class_list":["post-5461","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-uncategorized","tag-dark-reading"],"featured_image_urls":{"full":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=1800%2C1013&ssl=1",1800,1013,false],"thumbnail":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?resize=150%2C150&ssl=1",150,150,true],"medium":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=300%2C169&ssl=1",300,169,true],"medium_large":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=640%2C360&ssl=1",640,360,true],"large":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=640%2C360&ssl=1",640,360,true],"1536x1536":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=1536%2C864&ssl=1",1536,864,true],"2048x2048":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=1800%2C1013&ssl=1",1800,1013,true],"chromenews-featured":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=1024%2C576&ssl=1",1024,576,true],"chromenews-large":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?resize=825%2C575&ssl=1",825,575,true],"chromenews-medium":["https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?resize=590%2C410&ssl=1",590,410,true]},"author_info":{"display_name":"Dark Reading","author_link":"https:\/\/ddi.mohflo.net\/index.php\/author\/darkreading\/"},"category_info":"Uncategorized<\/a>","tag_info":"Uncategorized","comment_count":"0","jetpack_featured_media_url":"https:\/\/i0.wp.com\/ddi.mohflo.net\/wp-content\/uploads\/2024\/09\/security-concerns-plague-emerging-chip-architecture.png?fit=1800%2C1013&ssl=1","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/posts\/5461","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/users\/12"}],"replies":[{"embeddable":true,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/comments?post=5461"}],"version-history":[{"count":0,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/posts\/5461\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/media\/5462"}],"wp:attachment":[{"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/media?parent=5461"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/categories?post=5461"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ddi.mohflo.net\/index.php\/wp-json\/wp\/v2\/tags?post=5461"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}